4 tms320c67x dsp architecture – Texas Instruments TMS320C67X/C67X+ DSP User Manual

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TMS320C67x DSP Architecture

1-7

Introduction

SPRU733

1.4 TMS320C67x DSP Architecture

Figure 1−1 is the block diagram for the C67x DSP. The C6000 devices come
with program memory, which, on some devices, can be used as a program
cache. The devices also have varying sizes of data memory. Peripherals such
as a direct memory access (DMA) controller, power-down logic, and external
memory interface (EMIF) usually come with the CPU, while peripherals such
as serial ports and host ports are on only certain devices. Check the data sheet
for your device to determine the specific peripheral configurations you have.

Figure 1−1. TMS320C67x DSP Block Diagram

БББ

256-bit data

32-bit address

Program cache/program memory

ББ

БББББ

ББББББББББББББББББББББ

8-, 16-, 32-bit data

32-bit address

Data cache/data memory

etc.

serial ports,

Timers,

Additional

peripherals:

down

Power

C6000 CPU

ББ

ББББББ

ББ

Interrupts

Emulation

Test

Control

logic

registers

Control

ББ

ББББББ

ББ

.D1

.M1

.S1

.L1

DMA, EMIF

.D2 .M2 .S2 .L2

Data path A

Data path B

Program fetch

Instruction decode

Instruction dispatch (See Note)