4 pipeline operation summary, Figure 4−5. pipeline phases – Texas Instruments TMS320C67X/C67X+ DSP User Manual

Page 338

Pipeline Operation Overview

Pipeline

4-6

SPRU733

4.1.4 Pipeline Operation Summary

Figure 4−5 shows all the phases in each stage of the C67x DSP pipeline in
sequential order, from left to right.

Figure 4−5. Pipeline Phases

Fetch

Execute

Decode

E10

Figure 4−6 shows an example of the pipeline flow of consecutive fetch packets
that contain eight parallel instructions. In this case, where the pipeline is full,
all instructions in a fetch packet are in parallel and split into one execute packet
per fetch packet. The fetch packets flow in lockstep fashion through each
phase of the pipeline.

For example, examine cycle 7 in Figure 4−6. When the instructions from FPn
reach E1, the instructions in the execute packet from FPn +1 are being
decoded. FP n + 2 is in dispatch while FPs n + 3, n + 4, n + 5, and n + 6 are
each in one of four phases of program fetch. See section 4.4, page 4-56, for
additional detail on code flowing through the pipeline. Table 4−1 summarizes
the pipeline phases and what happens in each phase.

Figure 4−6. Pipeline Operation: One Execute Packet per Fetch Packet

Clock cycle

Fetch

packet

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