3 execute – Texas Instruments TMS320C67X/C67X+ DSP User Manual
Page 337
Pipeline Operation Overview
4-5
Pipeline
SPRU733
4.1.3 Execute
The execute portion of the pipeline is subdivided into ten phases (E1−E10),
as compared to the five phases in a fixed-point pipeline. Different types of
instructions require different numbers of these phases to complete their
execution. These phases of the pipeline play an important role in your
understanding the device state at CPU cycle boundaries. The execution of dif-
ferent types of instructions in the pipeline is described in section 4.2, Pipeline
Execution of Instruction Types. Figure 4−4(a) shows the execute phases of
the pipeline in sequential order from left to right. Figure 4−4(b) shows the
portion of the functional block diagram in which execution occurs.
Figure 4−4. Execute Phases of the Pipeline
E4
E3
E2
E1
E5
(a)
(b)
Register file A
Register file B
Data 2
Data 1
32
32
32
32
(byte addressable)
Internal data memory
Data address 2
Data address 1
9
8
7
6
5
4
3
2
1
0
16
16
16
16
Data memory interface control
32
.L1
SADD
.S1
B
.M1
SMPY
0
1
3
5 4
2
6
8 7
10
12 11
9
14
15
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
.L2
SADD
.S2
SUB
SMPYH
.M2
Execute
E1
.D1
STH
.D2
STH
E9
E8
E7
E6
E10