Texas Instruments TMS320C67X/C67X+ DSP User Manual
Page 369
Functional Unit Constraints
4-37
Pipeline
SPRU733
Table 4−21 shows the instruction constraints for ADDSP/SUBSP instructions
executing on the .S unit.
Table 4−21. ADDSP/SUBSP .S-Unit Instruction Constraints
Instruction Execution
Cycle
1
2
3
4
ADDSP/SUBSP
R
W
Instruction Type
Subsequent Same-Unit Instruction Executable
Single-cycle
n
n
Xw
2-cycle DP
n
Xw
Xw
DP compare
n
Xw
n
ADDDP/SUBDP
n
n
n
ADDSP/SUBSP
n
n
n
Branch
n
n
n
Legend:
= E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
n
= Next instruction can enter E1 during cycle; Xw = Next instruction cannot enter E1 during cycle−write
constraint