Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 359)

Pipeline Execution of Instruction Types
4-27 Pipeline SPRU733
4.2.9 DP Compare Instructions
The DP compare instructions use the E1 and E2 phases of the pipeline to
complete their operations (see Table 4−11). The lower 32 bits of the sources
are read on E1, the upper 32 bits of the sources are read on E2, and the results
are written on E2. The following instructions are DP compare instructions:
- CMPEQDP
- CMPLTDP
- CMPGTDP
The DP compare instructions are executed on the .S unit. The functional unit
latency for DP compare instructions is 2. The status is written to the FAUCR
on E2. Figure 4−21 shows the fetch, decode, and execute phases of the pipe-
line that the DP compare instruction uses.
Table 4−11. DP Compare Instruction Execution
Pipeline Stage E1 E2
Read src1_l
src2_l src1_h
src2_h
Written dst
Unit in use .S .S
Figure 4−21. DP Compare Instruction Phases
PG PS PW PR DP DC E1 E2 1 delay slot