Texas Instruments TMS320C67X/C67X+ DSP - Manual (Page 21)

TMS320C67x DSP Features and Options
Introduction 1-4 SPRU733
1.3 TMS320C67x DSP Features and Options
The C6000 devices execute up to eight 32-bit instructions per cycle. The C67x
CPU consists of 32 general-purpose 32-bit registers and eight functional units.
These eight functional units contain:
- Two multipliers
- Six ALUs
The C6000 generation has a complete set of optimized development tools,
including an efficient C compiler, an assembly optimizer for simplified
assembly-language programming and scheduling, and a Windows™ based
debugger interface for visibility into source code execution characteristics. A
hardware emulation board, compatible with the TI XDS510™ and XDS560™
emulator interface, is also available. This tool complies with IEEE Standard
1149.1−1990, IEEE Standard Test Access Port and Boundary-Scan
Architecture.
Features of the C6000 devices include:
- Advanced VLIW CPU with eight functional units, including two multipliers
and six arithmetic units
J Executes up to eight instructions per cycle for up to ten times the
performance of typical DSPs
J Allows designers to develop highly effective RISC-like code for fast
development time
- Instruction packing
J Gives code size equivalence for eight instructions executed serially or
in parallel
J Reduces code size, program fetches, and power consumption
- Conditional execution of all instructions
J Reduces costly branching
J Increases parallelism for higher sustained performance
- Efficient code execution on independent functional units
J Industry’s most efficient C compiler on DSP benchmark suite
J Industry’s first assembly optimizer for fast development and improved
parallelization
- 8/16/32-bit data support, providing efficient memory support for a variety
of applications