Panasonic MN103001G/F01K - Manual (Page 422)

I/O Ports
15-56
15.12.3 Pin Configurations
Table 15-12-1 shows the pin configurations for port A.
Table 15-12-1 Port A Configuration
Port Pin PAn PAM = "1" PAM = "0"
No. PAnD = "1" PAnD = "0"
Port A 24 PA0 General-purpose General-purpose A0 Address output
output port input port <> * 1 <
23 PA1 General-purpose General-purpose A1 Address output
output port input port <> * 1 <
22 PA2 General-purpose General-purpose A2 Address output
output port input port <> * 1 <
20 PA3 General-purpose General-purpose A3 Address output
output port input port <> * 1 <
19 PA4 General-purpose General-purpose A4 Address output
output port input port <> * 1 <
18 PA5 General-purpose General-purpose A5 Address output
output port input port <> * 1 <
17 PA6 General-purpose General-purpose A6 Address output
output port input port <> * 1 <
16 PA7 General-purpose General-purpose A7 Address output
output port input port <> * 1 <
[Note 1]
: When reset (whether in address/data separate mode or address/data multiplex mode)
*1 : In the event of a reset in address/data multiplex mode , the PAPU bit in the PAMD register is set to
"1" and the address/data pins (the 8 bits ADM[7:0]) are pulled up.
<<>> : These pins are set in address/data multiplex mode.
[Note 2]
When the bus authority is granted, A7 to A0 (ADM7 to ADM0) go to high impedance.