Panasonic MN103001G/F01K - Manual (Page 306)

Serial Interface
13-4
• Parity None, 0 fixed, 1 fixed, even, odd
• Character length 7 bits, 8 bits
• Transmission and reception bit sequence
LSB or MSB selectable
• Clock source 1/8 or 1/32 of IOCLK
1/8 of timer 3 or timer 9 underflow
1/8 of external clock
• Maximum bit rate
19.2 kbit/s (when IOCLK is 15 MHz)
• Error detection during reception
Parity errors, overrun errors, framing errors
• Buffers Independent buffers for transmission and reception
Reception and transmission buffers are both double buffers
• Interrupts Transmission interrupts:
"Transmission end" or "transmission buffer empty" selectable
Reception interrupts:
"Reception end" or "reception end with error" selectable
• Master transmission, master reception possible (No start sequence conflict detection function)