Panasonic MN103001G/F01K - Manual (Page 16)

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List of Figures and Tables
List of Figures
1. General Specifications
Fig. 1-3-1 MN103001G Block Diagram .................................................................................... 1-4
Fig. 1-4-1 Pin Assignments Diagram ......................................................................................... 1-5
2. CPU
Fig. 2-2-1 CPU Core Block Diagram ......................................................................................... 2-3
Fig. 2-3-1 CPU Registers ........................................................................................................... 2-4
Fig. 2-3-2 Processor Status Word ............................................................................................... 2-5
Fig. 2-4-1 Little Endian Format ............................................................................................... 2-11
Fig. 2-5-1 Overview of the Interrupt System ........................................................................... 2-14
Fig. 2-5-2 Interrupt Control Register (GnICR) ........................................................................ 2-15
Fig. 2-5-3 Interrupt Accept Group Register ............................................................................. 2-17
Fig. 2-5-4 Interrupt Vector Address Register ........................................................................... 2-17
Fig. 2-5-5 Interrupt Sequence Flow ......................................................................................... 2-20
Fig. 2-5-6 Interrupt Sequence Flow ......................................................................................... 2-21
Fig. 2-5-7 Stack Frame Configuration ..................................................................................... 2-22
3. Extension Instruction Specifications
Fig. 3-1-1 Block Diagram of the Extension Function Unit ........................................................ 3-2
Fig. 3-2-1 Extension Block Register Set .................................................................................... 3-4
4. Memory Modes
Fig. 4-2-1 Memory Mode Pin Connection Diagram .................................................................. 4-3
Fig. 4-3-1 Memory Space in Extension Memory Mode ............................................................ 4-4
Fig. 4-3-2 Memory Space in Processor Mode ............................................................................ 4-5
5. Operating Mode
Fig. 5-1-1 Operating Mode Transition Diagram ........................................................................ 5-2
6. Clock Generator
Fig. 6-3-1 Clock Generator ........................................................................................................ 6-2
7. Internal Memory
Fig. 7-3-1 Internal Memory Block Diagram (In Memory Extension Mode) ............................. 7-3
8. Bus Controller (BC)
Fig. 8-3-1 Bus Configuration Diagram ...................................................................................... 8-3
Fig. 8-4-1 Block Diagram for the Bus Controller ...................................................................... 8-4