Panasonic MN103001G/F01K - Manual (Page 21)

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Fig. 14-5-2 External Trigger Input Conversion Example
(for Channels 0 to 2, One Time Each) ..................................................................... 14-8
Fig. 14-5-3 External Trigger Input Conversion Example .......................................................... 14-9
Fig. 14-5-4 External Trigger Input Conversion Example
(for Channels 0 to 2, Continuous Conversion) ...................................................... 14-10
Fig. 14-5-5 Conversion Timing When Using Two Sampling Cycles ...................................... 14-11
Fig. 14-5-6 Conversion Timing When Using Four Sampling Cycles ...................................... 14-11
Fig. 14-5-7 Example of Conversion by Switching to
External Trigger Mode (Single Conversion) ......................................................... 14-12
Fig. 14-5-8 Example of Conversion by Switching to
External Trigger Mode (Continuous Conversion) ................................................. 14-12
15. I/O Ports
Fig. 15-2-1 Port 0 Block Diagram (P02) .................................................................................... 15-6
Fig. 15-2-2 Port 0 Block Diagram (P01, P00) ............................................................................ 15-7
Fig. 15-3-1 Port 1 Block Diagram (P17 to P12)....................................................................... 15-10
Fig. 15-3-2 Port 1 Block Diagram (P11, and P10) ................................................................... 15-11
Fig. 15-4-1 Port 2 Block Diagram (P27 to P20)....................................................................... 15-15
Fig. 15-5-1 Port 3 Block Diagram (P30) .................................................................................. 15-19
Fig. 15-6-1 Port 4 Block Diagram (P45 and P43) .................................................................... 15-22
Fig. 15-6-2 Port 4 Block Diagram (P44) .................................................................................. 15-23
Fig. 15-6-3 Port 4 Block Diagram (P42, P40) .......................................................................... 15-24
Fig. 15-6-4 Port 4 Block Diagram (P41) .................................................................................. 15-24
Fig. 15-7-1 Port 5 Block Diagram (P55) .................................................................................. 15-29
Fig. 15-7-2 Port 5 Block Diagram (P54) .................................................................................. 15-30
Fig. 15-7-3 Port 5 Block Diagram (P53) .................................................................................. 15-31
Fig. 15-7-4 Port 5 Block Diagram (P52, P50) .......................................................................... 15-32
Fig. 15-7-5 Port 5 Block Diagram (P51) .................................................................................. 15-33
Fig. 15-8-1 Port 6 Block Diagram (P63 to P60)....................................................................... 15-38
Fig. 15-9-1 Port 7 Block Diagram (P73) .................................................................................. 15-41
Fig. 15-9-2 Port 7 Block Diagram (P72 to P70)....................................................................... 15-41
Fig. 15-10-1 Port 8 Block Diagram (P83 to P80)....................................................................... 15-45
Fig. 15-11-1 Port 9 Block Diagram (P97) .................................................................................. 15-48
Fig. 15-11-2 Port 9 Block Diagram (P96) .................................................................................. 15-48
Fig. 15-11-3 Port 9 Block Diagram (P95, P91, P90) ................................................................. 15-49
Fig. 15-11-4 Port 9 Block Diagram (P94, P93, P92) ................................................................. 15-49
Fig. 15-12-1 Port A Block Diagram (PA7 to PA0) .................................................................... 15-53
Fig 15-13-1 Port B Block Diagram (PB7 to PB0)..................................................................... 15-57
Fig 15-14-1 Port C Block Diagram (PC3 to PC0)..................................................................... 15-61
16. Internal Flash Memory
Fig. 16-3-1 Flash Memory Block Diagram ................................................................................ 16-2
Fig. 16-5-1 MN1030F01K Pin Assignments in Flash Memory Mode ....................................... 16-4
Fig. 16-5-2 Flash Memory Erasure Blocks ................................................................................ 16-7