Panasonic MN103001G/F01K - Manual (Page 419)

I/O Ports
15-53
15.12 Port A
15.12.1 Block Diagram
Fig. 15-12-1 shows a block diagram for port A.
Fig. 15-12-1 Port A Block Diagram (PA7 to PA0)
Internal data bus
M
P
X PAn
(n=7,6,5,4,3,2,1,0)
PAOUT
A7(n=7)
to A0(n=0)
PAM
PAMD
PADIR
PAnD
PAnO
P... Represents one bit of each register.
M
P
X
PAPU
PAnI
PAIN
A7 to A0
Output enable
signal
ADM7(n=7)
to ADM0(n=0)
or