Panasonic MN103001G/F01K - Manual (Page 201)

Interrupt Controller
9-13
Group 5 interrupt control register
Register symbol: G5ICR
Address: x'34000114
Purpose: This register is used to enable group 5 interrupts, and to confirm interrupt requests and detection.
Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit - G5 G5 G5 - T10B T10A T10U - T10B T10A T10U - T10B T10A T10U
name LV2 LV1 LV0 IE IE IE IR IR IR ID ID ID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Bit No. Bit name Description
0 T10UID Timer 10 overflow interrupt detection flag
0: No interrupt detected 1: Interrupt detected
1 T10AID Timer 10 compare/capture A interrupt detection flag
0: No interrupt detected 1: Interrupt detected
2 T10BID Timer 10 compare/capture B interrupt detection flag
0: No interrupt detected 1: Interrupt detected
3 — "0" is returned when this bit is read.
4 T10UIR Timer 10 overflow interrupt request flag
0: No interrupt request 1: Interrupt request
5 T10AIR Timer 10 compare/capture A interrupt request flag
0: No interrupt request 1: Interrupt request
6 T10BIR Timer 10 compare/capture B interrupt request flag
0: No interrupt request 1: Interrupt request
7 — "0" is returned when this bit is read.
8 T10UIE Timer 10 overflow interrupt enable flag
0: Disabled 1: Enabled
9 T10AIE Timer 10 compare/capture A interrupt enable flag
0: Disabled 1: Enabled
10 T10BIE Timer 10 compare/capture B interrupt enable flag
0: Disabled 1: Enabled
11 — "0" is returned when this bit is read.
12 G5LV0 Group 5 interrupt priority level register (LSB)
13 G5LV1 Group 5 interrupt priority level register
14 G5LV2 Group 5 interrupt priority level register (MSB)
Set a level from 6 to 0.
15 — "0" is returned when this bit is read.