Panasonic MN103001G/F01K - Manual (Page 12)

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8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode ...................................................................... 8-35
8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data
Separate Mode ............................................................................................ 8-37
8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode
and in Address/Data Separate Mode ........................................................... 8-39
8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Separate Mode ...................................................................... 8-41
8.13.6 8-bit Bus in Asynchronous Mode and in Address/Data
Separate Mode ............................................................................................ 8-45
8.13.7 16-bit Bus with Fixed Wait States, in Synchronous Mode
and in Address/Data Multiplex Mode ......................................................... 8-46
8.13.8 16-bit Bus with Handshaking, in Synchronous Mode and
in Address/Data Multiplex Mode ................................................................ 8-48
8.13.9 16-bit Bus in Asynchronous Mode and in Address/Data
Multiplex Mode .......................................................................................... 8-51
8.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode
and in Address/Data Multiplex Mode ......................................................... 8-52
8.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in
Address/Data Multiplex Mode .................................................................... 8-56
8.13.12 8-bit Bus in Asynchronous Mode and in Address/Data
Multiplex Mode .......................................................................................... 8-60
8.14 External Memory Space Access (DRAM Space) ........................................................ 8-62
8.14.1 DRAM Space .............................................................................................. 8-62
8.14.2 DRAM page mode ...................................................................................... 8-65
8.14.3 Software Page Mode ................................................................................... 8-66
8.14.4 DRAM refresh ............................................................................................ 8-68
8.15 Bus Arbitration ............................................................................................................. 8-70
8.16 Cautions ....................................................................................................................... 8-73
9. Interrupt Controller
9.1 Overview ........................................................................................................................ 9-2
9.2 Features .......................................................................................................................... 9-2
9.3 System Diagram ............................................................................................................. 9-2
9.4 Block Diagram ............................................................................................................... 9-3
9.5 Description of Registers ................................................................................................. 9-6
9.6 Description of Operation .............................................................................................. 9-30
10. 8-bit Timers
10.1 Overview ...................................................................................................................... 10-2
10.2 Features ........................................................................................................................ 10-2
10.3 Block Diagram ............................................................................................................. 10-3
10.4 Functions ...................................................................................................................... 10-9
10.5 Description of Registers ............................................................................................. 10-10