Siemens ERTEC200 - Manual (Page 80)

7.5.2 LBU Write to ERTEC 200 with separate Read/Write line (LBU_RDY_N active low)
LBU_CS_R_N/
LBU_CD_M_N
LBU_WR_N
LBU_A(20:0)/
LBU_SEG(1:0)
LBU_BE(1:0)_N
LBU_RDY_N
LBU_D(15:0)
t
CSWS
t
AWS
t
WRE
t
WDV
t
WDH
t
WAH
t
WCSH
t
RTW
t
RAP
t
WR
Figure 14: LBU-Write-Sequence with separate RD/WR line
Parameter Description Min Max
t
CSWS
chip select asserted to write pulse asserted delay 0 ns
t
AWS
address valid to write pulse asserted setup time 0 ns
t
WRE
write pulse asserted to ready enabled delay 5 ns 12 ns
t
WDV
write pulse asserted to data valid delay 40 ns
t
RAP
ready active pulse width 17 ns 23 ns
t
WCSH
write pulse deasserted to chip select deasserted delay 0 ns
t
WAH
address valid to write pulse deasserted hold time 0 ns
t
RTW
ready asserted to write pulse deasserted delay 0 ns
t
WDH
data valid/enabled to read pulse deasserted hold time 0 ns
t
WR
write recovery time 25 ns
Table 26: LBU Write access timing with seperate Read/Write line
Copyright © Siemens AG 2007. All rights reserved. 80 ERTEC 200 Manual
Technical data subject to change Version 1.1.0