Siemens ERTEC200 - Manual (Page 67)

5.3 Address Sp
Monitoring mechan egal accesses, and
timeout. The followi
• AHB
bus
• APB
bus
• EMIF
5.3.1 AHB Bus Mo
Separate address space mo DMA, LBU). If an AHB
master addresses an un e and an FIQ2 interrupt
is triggered at the ARM9 AHB_ADR system
control register and the associated access type (read, write, HTRANS, HSIZE) is stored in the QVZ_AHB_CTRL system
control register. The master that caused the access error is stored in the QVZ_AHB_M system control register.
In the case of an access violation by LBU as an AHB master, an interrupt request is also enabled and stored in the IRT
switch. The LBU interrupt LBU_IRQ0_N is output on the LBU bus.
If more than one AHB master causes an access violation simultaneously (accurate within one AHB clock cycle), only the
violation of the highest priority AHB master is indicated in the registers (see Section 3.1.1).
Diagnostic registers QVZ_AHB_ADR, QVZ_AHB_CTRL, and QVZ_AHB_M remain locked for subsequent access
violations until the QVZ_AHB_CTRL register has been read.
5.3.2 APB Bus Monitoring
The APB address space is monitored on the APB bus. If incorrect addressing is detected in the APB address space,
access to the APB side and AHB side is terminated with an "OKAY" response because the APB bus does not recognize
response-type signaling. An FIQ1 interrupt is triggered on the ARM946 interrupt controller. The incorrect access address
is placed in the QVZ_APB_ADR system control register. The QVZ_APB_ADR system control register is locked for
subsequent address violations until it has been read.
5.3.3 EMIF Monitoring
In the case of the EMIF, the external RDY_PER_N ready signal is monitored. In order to enable monitoring,
"Extended_Wait_Mode" must be switched on in the Async_Bank_0_Config to Async_Bank_3_Config configuration
registers. If one of the four memory areas that are selected via the CS_PER0_N to CS_PER3_N chip select outputs is
addressed, the memory controller of the ERTEC 200 waits for the RDY_PER_N input signal. The monitoring duration is
set in the ASYNC_WAIT_CYCLE_CONFIG EMIF register and is active if timeout monitoring (Bit 7) is set in the
EXTENDED_CONFIG EMIF register. The specified value (maximum of 255) multiplied by 16 AHB clock cycles yields the
monitoring time, i.e., the time that the memory controller waits for the Ready signal. After this time elapses, a Ready
signal is generated for the memory controller and an FIQ3 interrupt is generated for the ARM946 interrupt controller. In
addition, the address of the incorrect access is stored in the QVZ_EMIF_ADR system control register. The
QVZ_EMIF_ADR system control register is locked for subsequent address violations until it has been read.
The set FIQ3 interrupt is then removed if timeout monitoring is reset.
5.4 Configuration Options on the ERTEC 200
EMIF pins, which are stored in a SER_Con_REG SYSTEM CONTROL register during an active RESET_N PowerOn
reset, are present for setting various operating modes. These pins are available as EMIF pins during normal operation.
CONFIG[1]
Æ Enable/disable REF_CLK output
CONFIG[2] Æ Enable/disable LBU function
CONFIG[4,3] Æ Select 50/100/150 Mhz clock frequency for ARM946E-S
CONFIG[6,5] Æ If LBU is disabled: PHY debug, GPIO[44:32], select ETM9 on LBU port
ace and Timeout Monitoring
isms are incorporated in the ERTEC 200 for detection of incorrect addressing, ill
ng I/O are monitored:
nitoring
nitoring is assigned for each of the four AHB masters (ARM946, IRT,
used address space, the access is acknowledged with an error respons
46 interrupt controller. The incorrect access address is stored in the QVZ_
Copyright © Siemens AG 2007. All rights reserved. 67 ERTEC 200 Manual
Technical data subject to change Version 1.1.0