Siemens ERTEC200 - Manual (Page 6)

4.4.2 F-Timer Register Description ......................................................................................................... 44
4.5 Watchdog Timers ................................................................................................................................... 45
4.5.1 Watchdog Timer 0.......................................................................................................................... 45
4.5.2 Watchdog Timer 1.......................................................................................................................... 45
4.5.3 Watchdog Interrupt ........................................................................................................................ 45
4.5.4 WDOUT0_N................................................................................................................................... 45
4.5.5 WDOUT1_N................................................................................................................................... 45
4.5.6 Watchdog Registers....................................................................................................................... 46
4.5.7 Address Assignment of Watchdog Registers................................................................................. 46
4.5.8 Watchdog Register Description ..................................................................................................... 46
4.6 UART Interface....................................................................................................................................... 48
4.6.1 Address Assignment of UART Registers ....................................................................................... 49
4.6.2 UART Register Description............................................................................................................ 50
4.7 Synchronous Interface SPI..................................................................................................................... 54
4.7.1 Address Assignment of SPI Register ............................................................................................. 55
4.7.2 SPI Register Description................................................................................................................ 56
4.8 System control register........................................................................................................................... 58
4.8.1 Address Assignment of System Control Registers ........................................................................ 58
4.8.2 System Control Register Description ............................................................................................. 59
5 General Hardware Functions ................................................................................................64
5.1 Clock Generation and Clock Supply....................................................................................................... 64
5.1.1 Clock Supply in ERTEC 200 .......................................................................................................... 64
5.1.2 JTAG Clock Supply........................................................................................................................ 65
5.1.3 Clock Supply for PHYs and Ethernet MACs .................................................................................. 65
5.2 Reset Logic of the ERTEC 200 .............................................................................................................. 65
5.2.1 PowerOn reset ............................................................................................................................... 65
5.2.2 Hardware Reset ............................................................................................................................. 66
5.2.3 Watchdog Reset ............................................................................................................................ 66
5.2.4 Software reset................................................................................................................................ 66
5.2.5 IRT Switch Reset ........................................................................................................................... 66
5.3 Address Space and Timeout Monitoring ................................................................................................ 67
5.3.1 AHB Bus Monitoring....................................................................................................................... 67
5.3.2 APB Bus Monitoring....................................................................................................................... 67
5.3.3 EMIF Monitoring ............................................................................................................................ 67
5.4 Configuration Options on the ERTEC 200.............................................................................................. 67
6 External Memory Interface (EMIF) ........................................................................................69
6.1 Address Assignment of EMIF Registers................................................................................................. 70
6.2 EMIF Register Description ..................................................................................................................... 70
7 Local Bus Unit (LBU). ............................................................................................................74
7.1 Page Range Setting ............................................................................................................................... 76
7.2 Page Offset Setting ................................................................................................................................ 76
7.3 LBU Address Mapping ........................................................................................................................... 77
7.4 Page Control Setting .............................................................................................................................. 78
7.5 Host Access to the ERTEC200 .............................................................................................................. 78
7.5.1 LBU Read from ERTEC 200 with separate Read/Write line (LBU_RDY_N active low) ................. 79
7.5.2 LBU Write to ERTEC 200 with separate Read/Write line (LBU_RDY_N active low)...................... 80
7.5.3 LBU Read from ERTEC 200 with common Read/Write line (LBU_RDY_N active low) ................. 81
7.5.4 LBU Write to ERTEC 200 with common Read/Write line (LBU_RDY_N active low) ...................... 82
7.6 Host Interrupt Handling: ......................................................................................................................... 82
7.7 Address Assignment of LBU Registers .................................................................................................. 83
7.8 LBU Register Description ....................................................................................................................... 83
8 DMA-Controller.......................................................................................................................85
8.1 DMA Register Address Assignment ....................................................................................................... 86
8.2 Description of DMA Registers ................................................................................................................ 86
9 Multiport Ethernet PHY ..........................................................................................................88
10 Memory Description...............................................................................................................91
10.1 Memory Partitioning of the ERTEC 200 ................................................................................................. 91
10.2 Detailed Memory Description ................................................................................................................. 92
11 Test and Debugging...............................................................................................................94
11.1 ETM9 Embedded Trace Macrocell ......................................................................................................... 94
11.1.1 Trace Modes .................................................................................................................................. 94
11.1.2 Features of the ETM9 Module ....................................................................................................... 94
Copyright © Siemens AG 2007. All rights reserved. Page 6 ERTEC 200 Manual
Technical data subject to change Version 1.1.0