Siemens ERTEC200 - Manual (Page 8)

List of Figures
Figure 1: ERTEC 200 Block Diagram .................................................................................................................... 10
Figure 2: ERTEC 200 Package Description .......................................................................................................... 11
Figure 3: Structure of ARM946E-S Processor System .......................................................................................... 21
Figure 4: GPIO Cell on GPIO Port [31:0] of the ERTEC 200................................................................................. 35
Figure 5: Block Diagram of F-Counter ................................................................................................................... 43
Figure 6: Watchdog Timing.................................................................................................................................... 45
Figure 7: Block Diagram of UART ......................................................................................................................... 48
Figure 8: Block Diagram of SPI ............................................................................................................................. 54
Figure 9: Clock Generation in ERTEC 200 ............................................................................................................ 64
Figure 10: Clock Supply of Ethernet Interface ....................................................................................................... 65
Figure 11: Power-Up Phase of the PLL ................................................................................................................. 66
Figure 12: Interconnection of Addresses between Host and ERTEC 200 LBU ..................................................... 77
Figure 13: LBU-Read-Sequence with separate RD/WR line ................................................................................. 79
Figure 14: LBU-Write-Sequence with separate RD/WR line.................................................................................. 80
Figure 15: LBU-Read-Sequence with common RD/WR line.................................................................................. 81
Figure 16: LBU-Write-Sequence with common RD/WR line .................................................................................. 82
List of Tables
Table 1: ERTEC 200 Pin Assignment and Signal Description ............................................................................... 19
Table 2: Overview of IRQ Interrupts ...................................................................................................................... 25
Table 3: Overview of FIQ Interrupts....................................................................................................................... 25
Table 4: Overview of Interrupt Control Register..................................................................................................... 27
Table 5: CP15 Registers - Overview ..................................................................................................................... 31
Table 6: Overview of AHB Master-Slave Access................................................................................................... 32
Table 7: Access Type and Data Width of the I/O................................................................................................... 33
Table 8: Selection of Download Source................................................................................................................. 34
Table 9: Overview of GPIO Registers.................................................................................................................... 36
Table 10: Overview of Timer Registers ................................................................................................................. 40
Table 11: Overview of F-Timer Registers .............................................................................................................. 44
Table 12: Overview of WD Registers..................................................................................................................... 46
Table 13: Baud Rates for UART at F
UARTCLK
=50 MHz ........................................................................................... 49
Table 14: Overview of UART Registers ................................................................................................................. 49
Table 15: Overview of SPI Registers..................................................................................................................... 55
Table 16: Overview of System Control Registers .................................................................................................. 59
Table 17: Overview of ERTEC 200 Clocks ............................................................................................................ 64
Table 18: Configurations for ERTEC 200 .............................................................................................................. 68
Table 19: Overview of EMIF Registers .................................................................................................................. 70
Table 20: Setting of Various Page Sizes ............................................................................................................... 76
Table 21: Setting of Various Offset Areas ............................................................................................................. 76
Table 22: Address Mapping from the Perspective of an External Host Processor on the LBU Port ...................... 77
Table 23: Summary of Accesses to Address Areas of ERTEC 200....................................................................... 78
Table 24: Host Access to Address Areas of ERTEC 200 ...................................................................................... 78
Table 25: LBU Read access timing with seperate Read/Write line........................................................................ 79
Table 26: LBU Write access timing with seperate Read/Write line ........................................................................ 80
Table 27: LBU Read access timing with common Read/Write line ........................................................................ 81
Table 28: LBU Write access timing with common Read/Write line ........................................................................ 82
Table 29: Overview of LBU Registers.................................................................................................................... 83
Table 30: DMA Transfer Modes............................................................................................................................. 85
Table 31: I/O Synchronization Signals................................................................................................................... 85
Table 32: Overview of DMA Registers................................................................................................................... 86
Table 33: Partitioning of Memory Areas ................................................................................................................ 91
Table 34: Detailed Description of Memory Segments............................................................................................ 93
Table 35: Pin Assignment of JTAG Interface......................................................................................................... 95
Copyright © Siemens AG 2007. All rights reserved. Page 8 ERTEC 200 Manual
Technical data subject to change Version 1.1.0