Zilog Z86193 - Manual (Page 91)

Z8
®
CPU
User Manual
UM001604-0108 Counters and Timers
84
The counter timers remain at rest as long as the Enable Count bits are 0. To enable count-
ing, the Enable Count bit (D
1
for T0 and D
3
for T1) must be set to 1. Counting actually
starts when the Enable Count bit is written by an instruction. The first decrement occurs
four internal clock periods after the Enable Count bit has been set. If T1 is configured to
use an external clock, the first decrement begins on the next clock period. The Load and
Enable Count bits can be set at the same time. For example, using the instruction:
OR TMR,#03h
sets both D0 and D1 of the TMR. This loads the initial values of PRE0 and T0 into their
respective counters and starts the count after the M2T2 machine state after the operand is
fetched (see
Figure 74 ).
Prescaler Operations
During counting, the programmed clock source drives the 6-bit Prescaler Counter. The
counter is counted down from the value specified by bits of the corresponding Prescaler
Register, PRE0 (bit 7 to bit 2) or PRE1 (bit 7 to bit 2; see
Figure 70 and Figure 71 on page
Figure 74. Starting The Count
Figure 75. Counting Modes
D0
(% F5; Write-Only)
Count Mode
Prescaler 0 Register
R245 PRE0
(% F3; Write-Only)
Prescaler 1 Register
R243 PRE1
0 = T
1
Single Pass
1 = T
1
Modulo-n
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
TMR is Written, Counter/Timer
First Decrement Occurs
Four Clock Periods Later
is Loaded
#03h is Fetched
M3 M1 M2 Mn