Zilog Z86193 - Manual (Page 63)

Z8
®
CPU
User Manual
UM001604-0108 Input/Output Ports
56
Port 3
General Port I/O
Port 3 differs structurally from Ports 0, 1, and 2. Port 3 lines are fixed as four inputs (P33–
P30) and four outputs (P37–P34) Port 3 does not have an input and output register for each
bit. Instead, all of the input lines have one input register, and all of the output lines have an
output register. Port 3 can be a CMOS- or TTL- compatible I/O port. Under software con-
trol, the lines can be configured as special control lines for handshake, comparator inputs,
SPI control, external memory status, or I/O lines for the on-board serial and timer facili-
ties.
Figure 44 on page 57 displays the block diagram of Port 3.
The inputs can be Schmitt-Triggered, level-shifted, or single-trip point buffered. In some
cases, the Z8
®
MCU may have autolatches hardwired on certain Port 3 inputs and Low-
EMI capabilities on the outputs. Refer to specific product specifications for exact input/
output buffer type features. Refer to the sections on counter/timers, Stop Mode Recovery,
serial I/O, comparators, and interrupts for more information on the relationships of Port 3
to that feature.