Zilog Z86193 - Manual (Page 40)

Z8
®
CPU
User Manual
UM001604-0108 Reset
33
Reset
This section describes the Z8 ® CPU reset conditions, reset timing, and register initializa-
tion procedures. Reset is generated by Power-On Reset (POR), Reset Pin, Watchdog
Timer (WDT), and Stop Mode Recovery.
A system reset overrides all other operating conditions and puts the Z8 CPU into a known
state. To initialize the chip’s internal logic, the RESET input must be held Low for at least
21 SCP or 5 XTAL clock cycles. The control register and ports are reset to their default
conditions after a POR, a reset from the RESET pin, or WDT time-out while in RUN
mode and HALT mode. The control registers and ports are not reset to their default condi-
tions after Stop Mode Recovery and WDT time-out while in STOP mode.
While RESET pin is Low, AS is output at the internal clock rate, DS is forced Low, and
R/W remains High. The program counter is loaded with
000Ch
. I/O ports and control reg-
isters are configured to their default reset state.
Resetting the Z8 CPU does not affect the contents of the general-purpose registers.
Reset Pin, Internal POR Operation
In some cases, the Z8 CPU hardware RESET pin initializes the control and peripheral reg-
isters, as listed in
Table 12 on page 34 through Table 15 on page 37. Specific reset values
are shown by 1 or 0, while bits whose states are unknown are indicated by the letter U.
Table 12 on page 34 through Table 15 on page 37 list the reset conditions for the Z8 CPU.
The register file reset state is device dependent. Refer to the selected device product speci-
fications for register availability and reset state. Note: