Zilog Z86193 - Manual (Page 141)

Z8
®
CPU
User Manual
UM001604-0108 External Interface
134
Data Memory
The two Z8 external memory spaces, data and program, are addressed as two separate
spaces of up to 64 KB each. External Program Memory and external data memory are log-
ically selected by the data memory select output (DM). DM is made available on Port 3,
bit 4 (P34) by setting bit 4 and bit 3 in the Port 3 Mode Register (
F7h
) to 10 or 01 (see
Figure 125 ). DM is active Low during the execution of the LDE, LDEI instructions, and
High for the execution of program instructions. DM is also active Low during the execu-
tion of CALL, POP, PUSH, RET and IRET instructions if the stack resides in external data
memory. After a RESET, DM is not selected.
Bus Operation
Typical data transfers between Z8
®
CPU and external memory are displayed in Figure 126
on page 135 and Figure 127 on page 136. Machine cycles can vary from 6 to 12 clock
periods depending on the operation being performed. The notations used to describe the
basic timing periods of the Z8 CPU are machine cycles (Mn), timing states (Tn), and clock
periods. All timing references are made with respect to the output signals AS and DS. The
Figure 124. Z8 ® Stack Selection
Figure 125. Port 3 Data Memory Operation
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Port 0–1 Register
Register F8h (P01M)
Z8 Stack Selection
0 = External
1 = Internal
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Bits Configuration
00 P33 = Input P34 = Output
01 P33 = Input P34 = DM
Port 3 Mode Register
Register F7h (P3M)
10 P33 = Input P34 = DM
11 P33 = DAV1/RDY1 P34 = RDY1/DAV1