Zilog Z86193 - Manual (Page 48)

Z8
®
CPU
User Manual
UM001604-0108 Watchdog Timer
41
The WDTMR register is accessible only during the first 60 processor cycles from the exe-
cution of the first instruction after Power-On Reset, Watchdog Reset, or a Stop Mode
Recovery. After this point, the register cannot be modified by any means, intentional or
otherwise. The WDTMR is a write-only register.
WDTMR is located in ERF Bank F, register
0Fh
. This register’s control bits are described
on the next two pages.
WDT Time Select—Bits D1 and D0 control a tap circuit that determines the time-out
period.
Table 16 on page 41 lists the different values that can be obtained. The default val-
ues of D1 and D0 are 0 and 1, respectively.
WDT During HALT—The D2 bit determines whether or not the WDT is active during
HALT mode. A 1 indicates active during HALT. The default is 1. A WDT time out during
HALT mode resets control register ports to their default reset conditions.
WDT During STOP—The D3 bit determines whether or not the WDT is active during
STOP mode. Because XTAL clock is stopped during STOP mode, unless as specified
below, the on-board RC must be selected as the clock source to the POR counter. A 1 indi-
cates active during STOP. The default is 1. If bits D3 and D4 are both set to 1, the WDT
only, is driven by the external clock during STOP mode. This feature makes it possible to
wake up from STOP mode from an internal source. Refer to specific product specifica-
tions for conditions of control and port registers when the Z8
® CPU comes out of STOP
mode. A WDT time out during STOP mode does not reset all control registers. The reset
conditions of the ports from STOP mode due to WDT time out are the same as if recov-
ered using any of the other STOP mode sources.
Clock Source for WDT—The D4 bit determines which oscillator source is used to
clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator
is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1.
The default configuration of this bit is 0, which selects the internal RC oscillator.
Table 16. Time-Out Period of the WDT
Time-Out of
Typical Time-Out of Internal RC
OSC
System Clock D1 D0
0 0 5 ms min 256 TpC
0 1 15 ms min 512 TpC
1 0 25 ms min 1024 TpC
1 1 100 ms min 4096 TpC
Notes: The values given are for V
CC
= 5.0 V. See the device product specification for exact WDTMR
time out select options available.
1. TpC = XTAL clock cycle
2. The default on reset is, D0 = 1 and D1 = 0.