Zilog Z86193 - Manual (Page 128)

Z8
®
CPU
User Manual
UM001604-0108 Serial Input/Output
121
T0’s output drives a divide-by-16 counter that in turn generates a shift clock every 16
counts. This counter is reset when the transmitter buffer is written by an instruction. This
reset synchronizes the shift clock to the software. The transmitter then outputs one bit per
shift clock, through Port 3 bit 7, until a start bit, the character written to the buffer, and two
stop bits have been transmitted. After the second stop bit has been transmitted, the output
is again forced to a marking state. Interrupt request IRQ4 is generated at this time to notify
the processor that the transmitter is ready to accept another character.
Overwrites
The user is not protected from overwriting the transmitter, so it is up to the software to
respond to IRQ4 appropriately. If polling is used, the IRQ4 bit in the Interrupt Request
Register must be reset.
Parity
The data format supported by the transmitter has a start bit, eight data bits, and at least two
stop bits. If parity is on, bit 7 of the data transmitted will be replaced by an odd parity bit.
Figure 113 displays the transmitter data formats.
Parity is enabled by setting Port 3 Mode Register bit 7 to 1. If even parity is required,
PARITY mode should be disabled (P3M bit 7 reset to 0), and software must modify the
data to include even parity.
Because the transmitter can be overwritten, you can generate a break signal. This is done
by writing null characters to the transmitter buffer (SIO Register [
F0h
]) at a rate that does
not allow the stop bits to be output. Each time the SIO Register is loaded, the divide-by-16
counter is resynchronized and a new start bit is output followed by data.
Figure 113. Transmitter Data Formats
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Eight Data Bits
Start Bit
Start Bit
Seven Data Bits
Two Stop Bit
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Odd Parity
Two Stop Bit
Transmitted Data
(No Parity)
Transmitted Data
(With Parity)