Zilog Z86193 - Manual (Page 180)

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
173
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
destination Working Register operand is specified by adding
1110b
(
Eh
) to the high nibble
of the operand. For example, if Working Register R12 (CH) is the destination operand, then
ECh
is used as the destination operand in the Op Code.
Example 1
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum
is incorrect, however, when the binary representations are added in the destination location
using standard binary arithmetic.
0001 0101 = 15h
+ 0010 0111 = 27h
0011 1100 = 3Ch
If the result of the addition is stored in Register
5Fh
, the statement:
DA 5Fh
Op Code: 40 5F
adjusts this result so the correct BCD representation is obtained.
0011 1100 = 3Ch
0000 0110 = 06h
0100 0010 = 42h
Register
5Fh
now contains the value
42h
. The C, Z, and S Flags are cleared, and V is
undefined.
Example 2
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum
is incorrect, however, when the binary representations are added in the destination location
using standard binary arithmetic.
0001 0101 = 15h
+ 0010 0111 = 27h
Flag Description
C Set if there is a carry from the most significant bit; cleared
otherwise (see table above).
Z Set if the result is zero; cleared otherwise.
S Set if result bit 7 is set (negative); cleared otherwise.
D Unaffected
H Unaffected
E dst
Note: