Zilog Z86193 - Manual (Page 249)

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
242
Test Complement Under Mask
Syntax
TCM dst, src
Instruction Format
Operation
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical 1 value. The bits
to be tested are specified by setting a 1 bit in the corresponding bit position in the source
operand (the mask). The TCM instruction complements the destination operand, and then
ANDs it with the source mask (operand). The Zero (Z) Flag can then be checked to deter-
mine the result. If the Z Flag is set, then the tested bits were 1. When the TCM operation is
complete, the destination and source operands still contain their original values.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
source or destination Working Register operand is specified by adding
1110b
(
Eh
) to the
high nibble of the operand. For example, if Working Register R12 (CH) is the destination
operand, then
ECh
is used as the destination operand in the Op Code.
Cycles
OPC
(Hex)
Address Mode
dst src
OPC dst src
6 62 r r
6 63 r lr
OPC src dst
10 64 R R
10 65 R IR
OPC dst src
10 66 R IM
10 67 IR IM
Flag Description
Z Set if the result is zero; cleared otherwise.
S Set if the result bit 7 is set; cleared otherwise.
V Always reset to 0.
D Unaffected
H Unaffected
E src or E dst
Note: