Zilog Z86193 - Manual (Page 49)

Z8
®
CPU
User Manual
UM001604-0108 Watchdog Timer
42
Bits 5, 6, and 7—These bits are reserved.
V
CC
Voltage Comparator—An on-board voltage comparator checks that V
CC
is at the
required level to insure correct operation of the device. Reset is globally driven if V
CC
is
below the specified voltage. This feature is available in select ROM Z8 devices. See the
device product specification for feature availability and operating range.
Power-On Reset
A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On
Reset (POR) timer function, T
POR
. This POR time allows V
CC
and the oscillator circuit to
stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
Power fail to Power OK status (cold start)
•
Stop Mode Recovery (if bit 5 of SMR = 1)
•
WDT time-out
The POR time is specified as T
POR
. On Z8 devices that feature a Stop Mode Recovery
register (SMR), bit 5 selects whether the POR timer is used after Stop Mode Recovery or
by-passed. If bit D5 = 1 then the POR timer is used. If bit 5 = 0 then the POR timer is by-
passed. In this case, the Stop Mode Recovery source must be held in the recovery state for
5 T
P
C or 5 crystal clocks to pass the reset signal internally. This option is used when the
clock is provided with an RC/LC clock. See the device product specification for timing
details.
POR (cold start) always resets the Z8
®
CPU control and port registers to their default con-
dition. If a Z8 has a SMR, the warm start bit is reset to a 0 to indicate POR.
Figure 27. Example of Z8 with Simple SMR and POR
INT OSC
Chip
POR
Reset
P27
(Stop Mode)
(Cold Start)
VBO
WDT
Delay Line
T
POR
ms
18 CLK
Reset Filter
XTAL OSC