Zilog Z86193 - Manual (Page 42)

Z8
®
CPU
User Manual
UM001604-0108 Reset
35
After a reset, the first routine executed should be one that initializes the control registers to
the required system configuration.
The RESET pin is the input of a Schmitt-Triggered circuit. Resetting the Z8
®
CPU initial-
izes port and control registers to their default states. To form the internal reset line, the out-
put of the trigger is synchronized with the internal clock. The clock must therefore be
running for RESET to function. It requires 4 internal system clocks after reset is detected
for the Z8 CPU to reset the internal circuitry. An internal pull-up, combined with an exter-
nal capacitor of 1
µ F, provides enough time to properly reset the Z8 CPU (see Figure 23 on
page 36). In some cases, the Z8 CPU has an internal POR timer circuit that holds the Z8
CPU in reset mode for a duration (T
POR
) before releasing the device out of reset. On these
Z8 devices, the internally generated reset drives the reset pin low for the POR time. Any
devices driving the reset line must be open-drained in order to avoid damage from possible
conflict during reset conditions. This reset time allows the on-board clock oscillator to sta-
bilize.
To avoid asynchronous and noisy reset problems, the Z8 CPU is equipped with a reset fil-
ter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration,
no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is
latched and held for an internal register count of 18 external clocks, or for the duration of
the external reset, whichever is longer. During the reset cycle, DS is held active low while
AS cycles at a rate of the internal system clock. Program execution begins at location
000Ch
, 5-10 TpC cycles after RESET is released. For the internal Power-On Reset, the
reset output time is specified as T
POR
. Refer to specific product specifications for actual
values.
Figure 22. Reset Timing
First Machine Cycle
T1
Clock
RESET
AS
DS
R/W
First Instruction Fetch
Hold Low For 4 SCLK
Periods (Minimum)
SCLK