Zilog Z86193 - Manual (Page 214)

Z8
®
CPU
User Manual
UM001604-0108 Instruction Description
207
Logical OR
Syntax
OR dst, src
Instruction Format
Operation
dst
←
dst OR src
The source operand is logically ORed with the destination operand and the result is stored
in the destination operand. The contents of the source operand are not affected. The OR
operation results in a one bit being stored whenever either of the corresponding bits in the
two operands is a one. Otherwise, a zero bit is stored.
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
source or destination Working Register operand is specified by adding
1110b
(
Eh
) to the
high nibble of the operand. For example, if Working Register R12 (
Ch
) is the destination
operand, then
ECh
is used as the destination operand in the Op Code.
Cycles
OPC
(Hex)
Address
Mode
dst src
OPC dst src
6 02 r r
6 03 r lr
OPC src dst
10 04 R R
10 05 R IR
OPC dst src
10 06 R IM
10 07 IR IM
Flag Description
C Unaffected
Z Set if the result is zero; cleared otherwise
S Set if the result of bit 7 is set; cleared otherwise
V Always reset to 0
D Unaffected
H Unaffected
E src or E dst
Note: