Zilog Z86193 - Manual (Page 106)

Z8
®
CPU
User Manual
UM001604-0108 Interrupts
99
At sample time the request is transferred to the second flip-flop in Figure 94 , that drives
the interrupt mask and priority logic. When an interrupt cycle occurs, this flip-flop is reset
only for the highest priority level that is enabled.
You have direct access to the second flip-flop by reading and writing the IRQ Register.
IRQ is read by specifying it as the source register of an instruction and written by specify-
ing it as the destination register.
Interrupt Initialization
After reset, all interrupts are disabled and must be initialized before vectored or polled
interrupt processing can begin. The Interrupt Priority Register (IPR), Interrupt Mask Reg-
ister (IMR), and Interrupt Request Register (IRQ) must be initialized, in that order, to start
the interrupt process.
Figure 94. IRQ Register Logic
Figure 95. Interrupt Request Timing
Q
S
From
To Mask
IRQ0–IRQ5
R
Q
R
Priority
Logic
and
Priority
Logic
Sample
Clock
T1 T2 T3 T1 T2 T3 T1 T2 T3
External Interrupt
Interrupt Request
Sampled Internally
Request Sampled
Mn M1 M2