Zilog Z86193 - Manual (Page 44)

Z8
®
CPU
User Manual
UM001604-0108 Reset
37
Table 15. Sample Expanded Register File Bank F Reset Values
Register
(Hex)
Register Name
Bits
Comments 7 6 5 4 3 2 1 0
00 Port Configuration
(PCON) 1 1 1 1 1 1 1 0 Comparator outputs disabled on Port 3.
Port 0 and 1 output is push–pull.
Port 0, 1, 2, 3, and oscillator with
standard output drive.
0B Stop Mode
Recovery (SMR) 0 0 1 0 0 0 0 0 Clock divide by 16 off.
XTAL divide by 2.
POR and/OR External Reset.
Stop delay on.
Stop recovery level is low, STOP Flag
is POR.
0F Watchdog Timer
Mode (WDTMR) U U U 0 1 1 0 1 512 TPC for WDT time out, WDT runs
during STOP.