Zilog Z86193 - Manual (Page 145)

Z8
®
CPU
User Manual
UM001604-0108 External Interface
138
Timing is extended by setting bit D5 in the Port 0–1 Mode Register (
F8h
) to 1 (see
Figure 130 ). After a RESET, this bit is set to 0.
Instruction Timing
The High throughput of Z8 ® CPU is due, in part, to the use of an instruction pipeline, in
which the instruction fetch and execution cycles are overlapped. During the execution of
Figure 129. Extended External Memory Write Cycle
Figure 130. Extended Bus Timing
Machine Cycle
T2 TX T3
Clock
A15-A8
AD7–AD0
AS
DS
R/W
DM
Write Cycle
A15–A8
A7–A0 D7–D0 OUT
T1
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
Port 0–1 Register
Register F8h (P01M)
External Memory Timing
0 = Normal
1 = Extended