Zilog Z86193 - Manual (Page 47)

Z8
®
CPU
User Manual
UM001604-0108 Watchdog Timer
40
Watchdog Timer
The WDT is a retriggerable one-shot timer that resets the Z8 ® CPU if it reaches its termi-
nal count. When operating in the RUN or HALT modes, a WDT reset is functionally
equivalent to a hardware POR reset. The WDT is initially enabled by executing the WDT
instruction and refreshed on subsequent executions of the WDT instruction. The WDT
cannot be disabled after it has been initially enabled. Permanently enabled WDTs are
always enabled and the WDT instruction is used to refresh it. The WDT circuit is driven
by an on-board RC oscillator or external oscillator from the XTAL1 pin. The POR clock
source is selected with bit 4 of the Watchdog Timer Mode register (WDTMR). In some
cases, a Z8 that offers the WDT but does not have a WDTMR register, has a fixed WDT
time-out and uses the on board RC oscillator as the only clock source. Refer to specific
product specifications for selectability of time-out, WDT during HALT and STOP modes,
source of WDT clock, and availability of the permanently-on WDT option.
Execution of the WDT instruction affects the Z (zero), S (sign), and V (overflow) flags.
Figure 26. Example of Z8 Watchdog Timer Mode Register (Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDTMR (F) 0F
INT
00 5 128
01** 10 256
10 20 512
11 80 2048
WDT RC SYS
TAP* OSC CLK
WDT During STOP
0 OFF
1 ON *
WDT During HALT
0 OFF
1 ON *
XTAL1/INT RC
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
Select for WDT
* Must be 0 for Z86C03
** Default setting after RESET