Zilog Z86193 - Manual (Page 132)

Z8
®
CPU
User Manual
UM001604-0108 Serial Input/Output
125
SPI Operation
The SPI is used in one of two modes: either as system slave, or as system master. Several
of the possible system configurations are displayed in
Figure 117 on page 126. In slave
mode, data transfer starts when the slave select (SS) pin goes active. Data is transferred
into the slave’s SPI Shift Register through the DI pin, which has the same address as the
RxBUF Register. After a byte of data has been received by the SPI Shift Register, a
Receive Character Available (RCA/IRQ3) flag and interrupt is generated. The next byte of
data is received at this time. The RxBUF Register must be cleared, or a Receive Character
Overrun (RxCharOverrun) flag is set in the SCON Register, and the data in the RxBUF
Register is overwritten. When the communication between the master and slave is com-
plete, the SS goes inactive.When the SPI is activated as a slave, it operates in all system
modes: STOP, HALT, and RUN.
Unless disconnected, for every bit that is transferred into the slave through the DI pin, a bit
is transferred out through the D0 pin on the opposite clock edge. During slave operation,
the SPI clock pin (SK) is an input. In master mode, the CPU must first activate a SS
through one of its I/O ports. Next, data is transferred through the master’s D0 pin one bit
per master clock cycle. Loading data into the shift register initiates the transfer. In master
mode, the master’s clock drives the slave’s clock. At the conclusion of a transfer, a
Receive Character Available (RCA/IRQ3) flag and interrupt is generated. Before data is
transferred via the D0 pin, the SPI Enable bit in the SCON Register must be enabled.
SPI Compare
When the SPI Compare Enable bit, D3 of the SCON Register is set to 1, the SPI Compare
feature is enabled. The compare feature is only valid for slave mode. A compare transac-
tion begins when the (SS) line goes active. Data is received as if it were a normal transac-
tion, but there is no data transmitted to avoid bus contention with other slave devices.
When the compare byte is received, IRQ3 is not generated. Instead, the data is compared
with the contents of the SCOMP Register. If the data does not match, DO remains inactive
and the slave ignores all data until the (SS) signal is reset. If the data received matches the
data in the SCOMP register, then a SMR signal is generated. DO is activated if it is not tri-
stated by D2 in the SCON Register, and data is received the same as any other SPI slave
transaction.
Slaves’ not comparing remain in their current mode, whereas slaves’ comparing wake
from a STOP mode by means of an SMR
SPI Clock
The SPI clock may be driven by three sources: Timer0, a division of the internal system
clock, or the external master when in slave mode. Bit D6 of the SCON Register controls
what source drives the SPI clock. A 0 in bit D6 of the SCON Register determines the divi-