Zilog Z86193 - Manual (Page 41)

Z8
®
CPU
User Manual
UM001604-0108 Reset
34
Program execution starts 5 to 10 clock cycles after internal RESET has returned High. The
initial instruction fetch is from location
000Ch
. Figure 22 on page 35 displays reset tim-
ing.
Table 12. Sample Control and Peripheral Register Reset Values (ERF Bank 0)
Register
(Hex)
Register Name
Bits
Comments 7 6 5 4 3 2 1 0
F0 Serial I/O U U U U U U U U
F1 Timer Mode 0 0 0 0 0 0 0 0 Counter/Timers stopped.
F2 Counter/Timer1 U U U U U U U U
F3 T1 Prescaler U U U U U U 0 0 Single-pass count mode,
external clock source.
F4 Counter/Timer0 U U U U U U U U
F5 T0 Prescaler U U U U U U U 0 Single-pass count mode.
F6 Port 2 Mode 1 1 1 1 1 1 1 1 All inputs.
F7 Port 3 Mode 0 0 0 0 0 0 0 0 Port 2 open-drain, P33–P30
Input, P37–P34 Output.
F8 Port 0–1 Mode 0 1 0 0 1 1 0 1 Internal Stack, Normal Memory
Timing.
F9 Interrupt Priority U U U U U U U U
FA Interrupt Request 0 0 0 0 0 0 0 0 All Interrupts Cleared.
FB Interrupt Mask 0 U U U U U U U Interrupts Disabled.
FC Flags U U U U U U U U
FD Register Pointer 0 0 0 0 0 0 0 0
FE Stack Pointer (High) U U U U U U U U
FF Stack Pointer (Low) U U U U U U U U