Zilog Z86193 - Manual (Page 59)

Z8
®
CPU
User Manual
UM001604-0108 Input/Output Ports
52
Port 2
Port 2 is a general-purpose port. Figure 29 on page 45 displays a block diagram of Port 2.
Each of its lines can be independently programmed as input or output via the Port 2 Mode
Register (
F6h
) as seen in Figure 38 . A bit set to a 1 in P2M configures the corresponding
bit in Port 2 as an input, while a bit set to 0 configures an output line.
General Port I/O
Port 2 can be an 8-bit, bidirectional, CMOS- or TTL- compatible I/O port. These eight I/O
lines can be configured under software control to be an input or output, independently.
Input buffers can be Schmitt-Triggered, level-shifted, or a single trip point buffer and may
contain autolatches. Bits programmed as outputs may be globally programmed as either
push-pull or open-drain. Low-EMI output buffers can be globally programmed by the soft-
ware, an OTP program option, or as a ROM mask option. In addition, when the SPI is fea-
tured and enabled, P20 functions as data-in (DI), and P27 functions as data-out (DO).
Refer to specific product specifications for exact input/output buffer type features avail-
able. See
Figure 39 on page 53 through Figure 41 on page 54.
Figure 38. Port 2 I/O Mode Configuration
D7 D6 D5 D4 D3 D2 D1 D0
(Write-Only)
1 = Input
Port 2 Mode
0 = Output
Port 2 Mode Register (P2M)
Register F6h