Zilog Z86193 - Manual (Page 51)

Z8
®
CPU
User Manual
UM001604-0108 Input/Output Ports
44
Input and Output Registers
Each bit of Ports 0, 1, and 2, has an input register, an output register, associated buffer, and
control logic. Because there are separate input and output registers associated with each
port, writing to bits defined as inputs stores the data in the output register. This data cannot
be read as long as the bits are defined as inputs. However, if the bits are reconfigured as
outputs, the data stored in the output register is reflected on the output pins and can then be
read. This mechanism allows you to initialize the outputs prior to driving their loads (see
Figure 29 on page 45).
Because port inputs are asynchronous to the Z8
®
CPU internal clock, a READ operation
could occur during an input transition. In this case, the logic level might be uncertain
(between a logic 1 and 0). To eliminate this meta-stable condition, the Z8 CPU latches the
input data two clock periods prior to the execution of the current instruction. The input
register uses these two clock periods to stabilize to a legitimate logic level before the
instruction reads the data.
The following sections describe the generic function of the Z8 CPU ports. Any additional
features of the ports such as SPI, C/T, and Stop Mode Recovery are described in the respec-
tive sections.
Port 0
This section deals with only the I/O operation of Port 0. Figure 29 on page 45 displays a
block diagram of Port 0. This diagram also applies to Ports 1 and 2.
Note: