Zilog Z86193 - Manual (Page 35)

Z8
®
CPU
User Manual
UM001604-0108 Clock
28
Layout
Traces connecting crystal, caps, and the Z8 ® CPU oscillator pins should be as short and
wide as possible. This reduces parasitic inductance and resistance. The components (caps,
crystal, resistors) should be placed as close as possible to the oscillator pins of the Z8
CPU.
The traces from the oscillator pins of the IC and the ground side of the lead caps should be
guarded from all other traces (clock, V
CC
, address/data lines, system ground) to reduce
cross talk and noise injection. This is usually accomplished by keeping other traces and
system ground trace planes away from the oscillator circuit and by placing a Z8 CPU
device V
SS
ground ring around the traces/components. The ground side of the oscillator
lead caps should be connected to a single trace to the Z8 CPU’s V
SS
(GND) pin. It should
not be shared with any other system ground trace or components except at the Z8 CPU’s
V
SS
pin. This is to prevent differential system ground noise injection into the oscillator
(see Figure 17 on page 29).
Indications of an Unreliable Design
Start-up time and output level are two major indicators that are used in working designs to
determine their reliability over full lot and temperature variations. These two indicators
are described below.
Start-Up Time—If start-up time is excessive, or varies widely from unit to unit, there is
probably a gain problem. C1/C2 must be reduced; the amplifier gain is not adequate at fre-
quency, or crystal resistance is too large.
Output Level—The signal at the amplifier output should swing from ground to V
CC
.
This indicates there is adequate gain in the amplifier. As the oscillator starts up, the signal
amplitude grows until clipping occurs, at which point the loop gain is effectively reduced
to unity and constant oscillation is achieved. A signal of less than 2.5 V peak-to-peak is an
indication that low gain may be a problem. Either C
1
or C
2
should be made smaller or a
low-resistance crystal should be used.
Circuit Board Design Rules
The following circuit board design rules are suggested:
•
To prevent induced noise the crystal and load capacitors should be physically located
as close to the Z8 CPU as possible.
•
Signal lines should not run parallel to the clock oscillator inputs. In particular, the
crystal input circuitry and the internal system clock output should be separated as
much as possible.
•
V
CC
power lines should be separated from the clock oscillator input circuitry.
•
Resistivity between XTAL1 or XTAL2 and the other pins should be greater than 10
M
Ω.