Zilog Z86193 - Manual (Page 50)

Z8
®
CPU
User Manual
UM001604-0108 Input/Output Ports
43
Input/Output Ports
Z8 ® CPU features up to 32 lines dedicated to input and output. These lines are grouped
into four 8-bit ports known as Port 0, Port 1, Port 2, and Port 3. Port 0 is nibble program-
mable as input, output, or address. Port 1 is byte configurable as input, output, or address/
data. Port 2 is bit programmable as either inputs or outputs, with or without handshake and
SPI. Port 3 can be programmed to provide timing, serial and parallel input/output, or com-
parator input/output.
All ports have push–pull CMOS outputs. In addition, the push–pull outputs of Port 2 can
be turned OFF for open-drain operation.
Mode Registers
Each port has an associated Mode Register that determines the port’s functions and allows
dynamic change in port functions during program execution. Port and Mode Registers are
mapped into the Standard Register File as displayed in
Figure 28 .
Because of their close association, Port and Mode registers are treated like any other gen-
eral-purpose registers. There are no special instructions for port manipulation. Any
instruction which addresses a register can address the ports. Data can be directly accessed
in the Port Register, with no extra moves.
Figure 28. I/O Ports and Mode Registers
Register HEX
Port 3 Mode
Port 2 Mode
Identifier
F8h
F7h
F6h
P01M
P3M
P2M
Port 3
Port 0–1 Mode
Port 2
Port 1
Port 0
03h
02h
01h
00h
P3
P2
P1
P0