Flash, Flash –60 – Altera Stratix IV GX FPGA Development Board User Manual
Page 68
2–60
Chapter 2: Board Components
Memory
Stratix IV GX FPGA Development Board
August 2012
Altera Corporation
Reference Manual
lists the SSRAM component reference and manufacturing information.
Flash
The flash interface consists of a single synchronous flash memory device, providing
64 MB interface with a 16-bit data bus. This device is part of the shared FSM Bus,
which connects to flash memory, SSRAM, and the Max II CPLD EPM2210 System
Controller.
There are two 256 MB die per package with A(25) low selecting the lower die and
A(25) high selecting the upper die. Parameter blocks are 32 K and main blocks are
128 K. The parameters of this device are located at both the top and bottom of the
address space.
U30.N11
Data bus parity byte lane 0
SRAM_DQP0
2.5-V
F35
U30.C11
Data bus parity byte lane 1
SRAM_DQP1
2.5-V
AJ32
U30.C1
Data bus parity byte lane 2
SRAM_DQP2
2.5-V
N33
U30.N1
Data bus parity byte lane 3
SRAM_DQP3
2.5-V
AJ35
U30.B6
Clock
SRAM_CLK
2.5-V
AE26
U30.B8
Output enable
SRAM_OEn
2.5-V
AK34
U30.A3
Chip enable
SRAM_CEn
2.5-V
AT30
U30.B5
Byte lane 0 write enable
SRAM_BWn0
2.5-V
AH27
U30.A5
Byte lane 1 write enable
SRAM_BWn1
2.5-V
AR31
U30.A4
Byte lane 2 write enable
SRAM_BWn2
2.5-V
AH28
U30.B4
Byte lane 3 write enable
SRAM_BWn3
2.5-V
AL29
U30.A7
Byte write enable
SRAM_BWEn
2.5-V
AK30
U30.B7
Global write enable
SRAM_GWn
2.5-V
AC29
U30.A8
Address status controller
SRAM_ADSCn
2.5-V
AM31
U30.B9
Address status processor
SRAM_ADSPn
2.5-V
AG28
U30.A9
Address valid
SRAM_ADVn
2.5-V
AU32
U30.R1
Mode
SRAM_MODE
2.5-V
—
(Connects to the MAX II
CPLD EPM2210 System
Controller)
U30.H11
Sleep
SRAM_ZZ
2.5-V
AJ29
Table 2–54. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board Reference
Description
Schematic Signal Name
I/O Standard
Stratix IV GX Device
Pin Number
Table 2–55. SSRAM Component Reference and Manufacturing Information
Board Reference
Description
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U30
Standard synchronous pipelined
SCD, 512K × 36 bit, 250 MHz
ISSI Inc.
IS61VPS51236A-250B3