Altera Stratix IV GX FPGA Development Board - Manual (Page 60)

2–52 Chapter 2: Board Components
Memory
Stratix IV GX FPGA Development Board August 2012 Altera Corporation
Reference Manual
U14.R7 Address bus DDR3TOP_A11 1.5-V SSTL Class I A19
U14.L7 Address bus DDR3TOP_A10 1.5-V SSTL Class I B23
U14.R3 Address bus DDR3TOP_A9 1.5-V SSTL Class I M21
U14.T8 Address bus DDR3TOP_A8 1.5-V SSTL Class I F21
U14.R2 Address bus DDR3TOP_A7 1.5-V SSTL Class I M20
U14.R8 Address bus DDR3TOP_A6 1.5-V SSTL Class I G21
U14.P2 Address bus DDR3TOP_A5 1.5-V SSTL Class I P19
U14.P8 Address bus DDR3TOP_A4 1.5-V SSTL Class I D21
U14.N2 Address bus DDR3TOP_A3 1.5-V SSTL Class I R20
U14.P3 Address bus DDR3TOP_A2 1.5-V SSTL Class I N19
U14.P7 Address bus DDR3TOP_A1 1.5-V SSTL Class I C22
U14.N3 Address bus DDR3TOP_A0 1.5-V SSTL Class I D19
U14.M3 Bank address bus DDR3TOP_BA2 1.5-V SSTL Class I A14
U14.N8 Bank address bus DDR3TOP_BA1 1.5-V SSTL Class I E23
U14.M2 Bank address bus DDR3TOP_BA0 1.5-V SSTL Class I B14
U14.J3 Row address select DDR3TOP_RASn 1.5-V SSTL Class I A24
U14.T2 Reset DDR3TOP_RSTn 1.5-V SSTL Class I L20
U14.K3 Column address select DDR3TOP_CASn 1.5-V SSTL Class I B19
U14.L2 Chip select DDR3TOP_CSn 1.5-V SSTL Class I D15
U14.L3 Write enable DDR3TOP_WEn 1.5-V SSTL Class I C19
U14.K1 Termination enable DDR3TOP_ODT 1.5-V SSTL Class I K15
U14.K9 Clock enable DDR3TOP_CKE 1.5-V SSTL Class I A25
U14.J7 Clock P DDR3TOP_CK_P 1.5-V SSTL Class I D24
U14.K7 Clock N DDR3TOP_CK_N 1.5-V SSTL Class I C24
U14.E3 Data bus byte lane 0 DDR3TOP_DQ0 1.5-V SSTL Class I A10
U14.F7 Data bus byte lane 0 DDR3TOP_DQ1 1.5-V SSTL Class I D11
U14.F2 Data bus byte lane 0 DDR3TOP_DQ2 1.5-V SSTL Class I B10
U14.F8 Data bus byte lane 0 DDR3TOP_DQ3 1.5-V SSTL Class I C12
U14.H3 Data bus byte lane 0 DDR3TOP_DQ4 1.5-V SSTL Class I C11
U14.H8 Data bus byte lane 0 DDR3TOP_DQ5 1.5-V SSTL Class I C13
U14.G2 Data bus byte lane 0 DDR3TOP_DQ6 1.5-V SSTL Class I A11
U14.H7 Data bus byte lane 0 DDR3TOP_DQ7 1.5-V SSTL Class I B13
U14.E7 Write mask byte lane 0 DDR3TOP_DM0 1.5-V SSTL Class I B11
U14.F3 Data strobe P byte lane 0 DDR3TOP_DQS_P0 1.5-V SSTL Class I D14
U14.G3 Data strobe N byte lane 0 DDR3TOP_DQS_N0 1.5-V SSTL Class I C14
U14.D7 Data bus byte lane 1 DDR3TOP_DQ8 1.5-V SSTL Class I K22
U14.C3 Data bus byte lane 1 DDR3TOP_DQ9 1.5-V SSTL Class I D22
U14.C8 Data bus byte lane 1 DDR3TOP_DQ10 1.5-V SSTL Class I J22
Table 2–48. DDR3 Top Port Pin Assignments, Signal Names and Functions (Part 2 of 3)
Board Reference Description Schematic Signal
Name
I/O Standard
Stratix IV GX
Device
Pin Number