Altera Stratix IV GX FPGA Development Board - Manual (Page 65)

Chapter 2: Board Components 2–57
Memory
August 2012 Altera Corporation Stratix IV GX FPGA Development Board
Reference Manual
U7.M11 Write data bus QDR2TOP1_D2 1.5-V HSTL Class I N17
U7.N11 Write data bus QDR2TOP1_D1 1.5-V HSTL Class I M17
U7.P10 Write data bus QDR2TOP1_D0 1.5-V HSTL Class I P16
U7.B6 Write clock P QDR2TOP1_K_P 1.5-V HSTL Class I N16
U7.A6 Write clock N QDR2TOP1_K_N 1.5-V HSTL Class I M16
U7.A4 Write port select QDR2TOP1_WPSn 1.5-V HSTL Class I D18
U7.B7 Write byte write select 0 QDR2TOP1_BWSn0 1.5-V HSTL Class I H17
U7.A5 Write byte write select 1 QDR2TOP1_BWSn1 1.5-V HSTL Class I J17
U7.R6 Termination enable QDR2TOP1_ODT 1.5-V HSTL Class I C20
U7.P3 Read data bus QDR2TOP1_Q17 1.5-V HSTL Class I N13
U7.N3 Read data bus QDR2TOP1_Q16 1.5-V HSTL Class I N15
U7.L2 Read data bus QDR2TOP1_Q15 1.5-V HSTL Class I R14
U7.K3 Read data bus QDR2TOP1_Q14 1.5-V HSTL Class I P14
U7.G3 Read data bus QDR2TOP1_Q13 1.5-V HSTL Class I M14
U7.F2 Read data bus QDR2TOP1_Q12 1.5-V HSTL Class I N14
U7.E3 Read data bus QDR2TOP1_Q11 1.5-V HSTL Class I M13
U7.D3 Read data bus QDR2TOP1_Q10 1.5-V HSTL Class I K14
U7.B2 Read data bus QDR2TOP1_Q9 1.5-V HSTL Class I L14
U7.B11 Read data bus QDR2TOP1_Q8 1.5-V HSTL Class I E14
U7.C10 Read data bus QDR2TOP1_Q7 1.5-V HSTL Class I F14
U7.E11 Read data bus QDR2TOP1_Q6 1.5-V HSTL Class I F12
U7.F11 Read data bus QDR2TOP1_Q5 1.5-V HSTL Class I G14
U7.J10 Read data bus QDR2TOP1_Q4 1.5-V HSTL Class I H14
U7.K11 Read data bus QDR2TOP1_Q3 1.5-V HSTL Class I K12
U7.L11 Read data bus QDR2TOP1_Q2 1.5-V HSTL Class I J12
U7.M10 Read data bus QDR2TOP1_Q1 1.5-V HSTL Class I K13
U7.P11 Read data bus QDR2TOP1_Q0 1.5-V HSTL Class I J13
U7.A11 Read clock P QDR2TOP1_CQ_P 1.5-V HSTL Class I H13
U7.A1 Read clock N QDR2TOP1_CQ_N 1.5-V HSTL Class I L13
U7.A8 Read port select QDR2TOP1_RPSn 1.5-V HSTL Class I F19
U7.P6 Read data valid QDR2TOP1_QVLD 1.5-V HSTL Class I D13
U7.H1 DLL enable QDR2TOP1_DOFFn 1.5-V HSTL Class I D20
Table 2–52. QDRII+ Top Port 1 Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board Reference Description
Schematic Signal Name
I/O Standard
Stratix IV GX
Device
Pin Number