Altera Stratix IV GX FPGA Development Board User Manual
Page 21
Chapter 2: Board Components
2–13
Configuration, Status, and Setup Elements
August 2012
Altera Corporation
Stratix IV GX FPGA Development Board
Reference Manual
illustrates the JTAG chain.
Figure 2–4. JTAG Chain
Embedded
Blaster
GPIO
TCK
4SGX230
FPGA
Analog
Switch
EPM2210
System
Controller
HSMC
Port A
HSMC
Port B
GPIO
TMS
GPIO
TDO
GPIO
TDI
JTAG Master
GPIO
DISABLE
JTAG Master/Slave
JTAG Master/Slave
Installed
HSMC
Card
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
Analog
Switch
EPM2210_JTAG_EN
HSMA_JTAG_EN
HSMB_JTAG_EN
ALWAYS
ENABLED
(in chain)
SW6.1
SW6.2
SW6.3
SW4.2
10-pin
JTAG Header
Flash
Memory
(on install)
PCI Express
Edge
Connector
JTAG Master/Slave
PCI Express
Motherboard
TCK
TMS
TDI
TDO
Analog
Switch
PCIE_JTAG_EN
SW6.4
Embedded
Blaster
Connection
USB
PHY
J7
J8
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)