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Hsmc, Hsmc –34 – Altera Stratix IV GX FPGA Development Board User Manual

Page 42

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2–34

Chapter 2: Board Components

Components and Interfaces

Stratix IV GX FPGA Development Board

August 2012

Altera Corporation

Reference Manual

Table 2–35

lists the Ethernet PHY interface pin assignments.

Table 2–36

lists the Ethernet PHY interface component reference and manufacturing

information.

HSMC

The development board contains two HSMC interfaces, port A and port B. These
HSMC interfaces support both single-ended and differential signaling. The HSMC
interface also allows JTAG, SMB, clock outputs and inputs, as well as power for
compatible HSMC cards. The HSMC is an Altera-developed open specification, which
allows you to expand the functionality of the development board through the
addition of daughtercards.

f

For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the

High

Speed Mezzanine Card (HSMC) Specification

manual.

The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.

Table 2–35. Ethernet PHY Pin Assignments, Signal Names and Functions

Board Reference

Description

Schematic Signal

Name

I/O Standard

Stratix IV GX

Device

Pin Number

U21.82

SGMII TX data

ENET_TX_P

LVDS

L29

U21.81

SGMII TX data

ENET_TX_N

K29

U21.77

SGMII RX data

ENET_RX_P

AC31

U21.75

SGMII RX data

ENET_RX_N

AC32

U21.25

Management bus control

ENET_MDC

2.5-V

AH34

U21.24

Management bus data

ENET_MDIO

M33

U21.23

Management bus interrupt

ENET_INTn

R30

U21.28

Device reset

ENET_RESETn

V31

Table 2–36. Ethernet PHY Component Reference and Manufacturing Information

Board Reference

Description

Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U21

Ethernet PHY BASE-T device

Marvel
Semiconductor

88E1111-B2-CAAIC000

www.marvell.com