Altera Stratix IV GX FPGA Development Board - Manual (Page 44)

2–36 Chapter 2: Board Components
Components and Interfaces
Stratix IV GX FPGA Development Board August 2012 Altera Corporation
Reference Manual
J1.13 Transceiver TX bit 4 HSMA_TX_P4 1.4-V PCML AD4
J1.14 Transceiver RX bit 4 HSMA_RX_P4 1.4-V PCML AE2
J1.15 Transceiver TX bit 4n HSMA_TX_N4 1.4-V PCML AD3
J1.16 Transceiver RX bit 4n HSMA_RX_N4 1.4-V PCML AE1
J1.17 Transceiver TX bit 3 HSMA_TX_P3 1.4-V PCML AF4
J1.18 Transceiver RX bit 3 HSMA_RX_P3 1.4-V PCML AG2
J1.19 Transceiver TX bit 3n HSMA_TX_N3 1.4-V PCML AF3
J1.20 Transceiver RX bit 3n HSMA_RX_N3 1.4-V PCML AG1
J1.21 Transceiver TX bit 2 HSMA_TX_P2 1.4-V PCML AH4
J1.22 Transceiver RX bit 2 HSMA_RX_P2 1.4-V PCML AJ2
J1.23 Transceiver TX bit 2n HSMA_TX_N2 1.4-V PCML AH3
J1.24 Transceiver RX bit 2n HSMA_RX_N2 1.4-V PCML AJ1
J1.25 Transceiver TX bit 1 HSMA_TX_P1 1.4-V PCML AP4
J1.26 Transceiver RX bit 1 HSMA_RX_P1 1.4-V PCML AR2
J1.27 Transceiver TX bit 1n HSMA_TX_N1 1.4-V PCML AP3
J1.28 Transceiver RX bit 1n HSMA_RX_N1 1.4-V PCML AR1
J1.29 Transceiver TX bit 0 HSMA_TX_P0 1.4-V PCML AT4
J1.30 Transceiver RX bit 0 HSMA_RX_P0 1.4-V PCML AU2
J1.31 Transceiver TX bit 0n HSMA_TX_N0 1.4-V PCML AT3
J1.32 Transceiver RX bit 0n HSMA_RX_N0 1.4-V PCML AU1
J1.33 Management serial data HSMA_SDA 2.5-V AJ11
J1.34 Management serial clock HSMA_SCL L11
J1.35 JTAG clock signal FPGA_JTAG_TCK 2.5-V —
J1.36 JTAG mode select signal FPGA_JTAG_TMS 2.5-V —
J1.37 JTAG data output HSMA_JTAG_TDO 2.5-V —
J1.38 JTAG data input HSMA_JTAG_TDI 2.5-V —
J1.39 Dedicated CMOS clock out HSMA_CLK_OUT0 2.5-V AM29
J1.40 Dedicated CMOS clock in HSMA_CLK_IN0 2.5-V AB34
J1.41 Dedicated CMOS I/O bit 0 HSMA_D0 2.5-V AW10
J1.42 Dedicated CMOS I/O bit 1 HSMA_D1 2.5-V AV10
J1.43 Dedicated CMOS I/O bit 2 HSMA_D2 2.5-V AW7
J1.44 Dedicated CMOS I/O bit 3 HSMA_D3 2.5-V AV7
J1.47 LVDS TX bit 0 or CMOS bit 4 HSMA_TX_D_P0 LVDS or 2.5-V AN9
J1.48 LVDS RX bit 0 or CMOS bit 5 HSMA_RX_D_P0 LVDS or 2.5-V AT9
J1.49 LVDS TX bit 0n or CMOS bit 6 HSMA_TX_D_N0 LVDS or 2.5-V AP9
J1.50 LVDS RX bit 0n or CMOS bit 7 HSMA_RX_D_N0 LVDS or 2.5-V AU9
J1.53 LVDS TX bit 1 or CMOS bit 8 HSMA_TX_D_P1 LVDS or 2.5-V AN7
J1.54 LVDS RX bit 1 or CMOS bit 9 HSMA_RX_D_P1 LVDS or 2.5-V AT8
Table 2–37. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
Description
Schematic Signal
Name
I/O Standard
Stratix IV GX
Device
Pin Number