Altera Stratix IV GX FPGA Development Board - Manual (Page 57)

Chapter 2: Board Components 2–49
Memory
August 2012 Altera Corporation Stratix IV GX FPGA Development Board
Reference Manual
U5, U12, U18, U24 pin K7 Clock N DDR3BOT_CK_N 1.5-V SSTL Class I AF20
U5.E3 Data bus byte lane 0 DDR3BOT_DQ0 1.5-V SSTL Class I AM14
U5.F7 Data bus byte lane 0 DDR3BOT_DQ1 1.5-V SSTL Class I AM13
U5.F2 Data bus byte lane 0 DDR3BOT_DQ2 1.5-V SSTL Class I AN14
U5.F8 Data bus byte lane 0 DDR3BOT_DQ3 1.5-V SSTL Class I AL14
U5.H3 Data bus byte lane 0 DDR3BOT_DQ4 1.5-V SSTL Class I AR14
U5.H8 Data bus byte lane 0 DDR3BOT_DQ5 1.5-V SSTL Class I AN13
U5.G2 Data bus byte lane 0 DDR3BOT_DQ6 1.5-V SSTL Class I AP14
U5.H7 Data bus byte lane 0 DDR3BOT_DQ7 1.5-V SSTL Class I AP13
U5.E7 Write mask byte lane 0 DDR3BOT_DM0 1.5-V SSTL Class I AL13
U5.F3 Data strobe P byte lane 0 DDR3BOT_DQS_P0 1.5-V SSTL Class I AR13
U5.G3 Data strobe N byte lane 0 DDR3BOT_DQS_N0 1.5-V SSTL Class I AT13
U5.D7 Data bus byte lane 1 DDR3BOT_DQ8 1.5-V SSTL Class I AT12
U5.C3 Data bus byte lane 1 DDR3BOT_DQ9 1.5-V SSTL Class I AW14
U5.C8 Data bus byte lane 1 DDR3BOT_DQ10 1.5-V SSTL Class I AU12
U5.C2 Data bus byte lane 1 DDR3BOT_DQ11 1.5-V SSTL Class I AV14
U5.A7 Data bus byte lane 1 DDR3BOT_DQ12 1.5-V SSTL Class I AW11
U5.A2 Data bus byte lane 1 DDR3BOT_DQ13 1.5-V SSTL Class I AU14
U5.B8 Data bus byte lane 1 DDR3BOT_DQ14 1.5-V SSTL Class I AV11
U5.A3 Data bus byte lane 1 DDR3BOT_DQ15 1.5-V SSTL Class I AW12
U5.D3 Write mask byte lane 1 DDR3BOT_DM1 1.5-V SSTL Class I AU11
U5.C7 Data strobe P byte lane 1 DDR3BOT_DQS_P1 1.5-V SSTL Class I AV13
U5.B7 Data strobe N byte lane 1 DDR3BOT_DQS_N1 1.5-V SSTL Class I AW13
U12.E3 Data bus byte lane 2 DDR3BOT_DQ16 1.5-V SSTL Class I AT16
U12.F7 Data bus byte lane 2 DDR3BOT_DQ17 1.5-V SSTL Class I AW16
U12.F2 Data bus byte lane 2 DDR3BOT_DQ18 1.5-V SSTL Class I AN16
U12.F8 Data bus byte lane 2 DDR3BOT_DQ19 1.5-V SSTL Class I AV16
U12.H3 Data bus byte lane 2 DDR3BOT_DQ20 1.5-V SSTL Class I AP17
U12.H8 Data bus byte lane 2 DDR3BOT_DQ21 1.5-V SSTL Class I AT15
U12.G2 Data bus byte lane 2 DDR3BOT_DQ22 1.5-V SSTL Class I AR17
U12.H7 Data bus byte lane 2 DDR3BOT_DQ23 1.5-V SSTL Class I AU15
U12.E7 Write mask byte lane 2 DDR3BOT_DM2 1.5-V SSTL Class I AU16
U12.F3 Data strobe P byte lane 2 DDR3BOT_DQS_P2 1.5-V SSTL Class I AP16
U12.G3 Data strobe N byte lane 2 DDR3BOT_DQS_N2 1.5-V SSTL Class I AR16
U12.D7 Data bus byte lane 3 DDR3BOT_DQ24 1.5-V SSTL Class I AJ16
U12.C3 Data bus byte lane 3 DDR3BOT_DQ25 1.5-V SSTL Class I AM17
U12.C8 Data bus byte lane 3 DDR3BOT_DQ26 1.5-V SSTL Class I AH16
U12.C2 Data bus byte lane 3 DDR3BOT_DQ27 1.5-V SSTL Class I AL17
Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board Reference Description Schematic Signal
Name
I/O Standard
Stratix IV GX
Device
Pin Number