Altera Stratix IV GX FPGA Development Board - Manual (Page 58)

2–50 Chapter 2: Board Components
Memory
Stratix IV GX FPGA Development Board August 2012 Altera Corporation
Reference Manual
U12.A7 Data bus byte lane 3 DDR3BOT_DQ28 1.5-V SSTL Class I AG16
U12.A2 Data bus byte lane 3 DDR3BOT_DQ29 1.5-V SSTL Class I AH17
U12.B8 Data bus byte lane 3 DDR3BOT_DQ30 1.5-V SSTL Class I AG17
U12.A3 Data bus byte lane 3 DDR3BOT_DQ31 1.5-V SSTL Class I AK17
U12.D3 Write mask byte lane 3 DDR3BOT_DM3 1.5-V SSTL Class I AF17
U12.C7 Data strobe P byte lane 3 DDR3BOT_DQS_P3 1.5-V SSTL Class I AK16
U12.B7 Data strobe N byte lane 3 DDR3BOT_DQS_N3 1.5-V SSTL Class I AL16
U18.E3 Data bus byte lane 4 DDR3BOT_DQ32 1.5-V SSTL Class I AU23
U18.F7 Data bus byte lane 4 DDR3BOT_DQ33 1.5-V SSTL Class I AN23
U18.F2 Data bus byte lane 4 DDR3BOT_DQ34 1.5-V SSTL Class I AT23
U18.F8 Data bus byte lane 4 DDR3BOT_DQ35 1.5-V SSTL Class I AM23
U18.H3 Data bus byte lane 4 DDR3BOT_DQ36 1.5-V SSTL Class I AP23
U18.H8 Data bus byte lane 4 DDR3BOT_DQ37 1.5-V SSTL Class I AL22
U18.G2 Data bus byte lane 4 DDR3BOT_DQ38 1.5-V SSTL Class I AR23
U18.H7 Data bus byte lane 4 DDR3BOT_DQ39 1.5-V SSTL Class I AN22
U18.E7 Write mask byte lane 4 DDR3BOT_DM4 1.5-V SSTL Class I AM22
U18.F3 Data strobe P byte lane 4 DDR3BOT_DQS_P4 1.5-V SSTL Class I AT24
U18.G3 Data strobe N byte lane 4 DDR3BOT_DQS_N4 1.5-V SSTL Class I AU24
U18.D7 Data bus byte lane 5 DDR3BOT_DQ40 1.5-V SSTL Class I AR19
U18.C3 Data bus byte lane 5 DDR3BOT_DQ41 1.5-V SSTL Class I AP19
U18.C8 Data bus byte lane 5 DDR3BOT_DQ42 1.5-V SSTL Class I AP18
U18.C2 Data bus byte lane 5 DDR3BOT_DQ43 1.5-V SSTL Class I AN19
U18.A7 Data bus byte lane 5 DDR3BOT_DQ44 1.5-V SSTL Class I AT18
U18.A2 Data bus byte lane 5 DDR3BOT_DQ45 1.5-V SSTL Class I AU18
U18.B8 Data bus byte lane 5 DDR3BOT_DQ46 1.5-V SSTL Class I AW18
U18.A3 Data bus byte lane 5 DDR3BOT_DQ47 1.5-V SSTL Class I AT17
U18.D3 Write mask byte lane 5 DDR3BOT_DM5 1.5-V SSTL Class I AN18
U18.C7 Data strobe P byte lane 5 DDR3BOT_DQS_P5 1.5-V SSTL Class I AU17
U18.B7 Data strobe N byte lane 5 DDR3BOT_DQS_N5 1.5-V SSTL Class I AV17
U24.E3 Data bus byte lane 6 DDR3BOT_DQ48 1.5-V SSTL Class I AV26
U24.F7 Data bus byte lane 6 DDR3BOT_DQ49 1.5-V SSTL Class I AU25
U24.F2 Data bus byte lane 6 DDR3BOT_DQ50 1.5-V SSTL Class I AT25
U24.F8 Data bus byte lane 6 DDR3BOT_DQ51 1.5-V SSTL Class I AN25
U24.H3 Data bus byte lane 6 DDR3BOT_DQ52 1.5-V SSTL Class I AR25
U24.H8 Data bus byte lane 6 DDR3BOT_DQ53 1.5-V SSTL Class I AP24
U24.G2 Data bus byte lane 6 DDR3BOT_DQ54 1.5-V SSTL Class I AP25
U24.H7 Data bus byte lane 6 DDR3BOT_DQ55 1.5-V SSTL Class I AW26
U24.E7 Write mask byte lane 6 DDR3BOT_DM6 1.5-V SSTL Class I AN24
Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference Description Schematic Signal
Name
I/O Standard
Stratix IV GX
Device
Pin Number