Altera Stratix IV GX FPGA Development Board - Manual (Page 15)

Chapter 2: Board Components 2–7
MAX II CPLD EPM2210 System Controller
August 2012 Altera Corporation Stratix IV GX FPGA Development Board
Reference Manual
Migration Support
Although the target FPGA for this development board is the EP4SGX230KF40 device,
the first device released in this 40nm FPGA family, the board supports migration to
the largest Stratix IV GX device, the EP4SGX530KF40.
Table 2–5 describes the features of the Stratix IV GX EP4SGX530KF40 device.
The specific I/O resources available in the Stratix IV GX EP4SGX230KF40 device are
the same for the Stratix IV GX EP4SGX530KF40 device.
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temperature monitoring
■ Fan control
■ Virtual JTAG interface for PC-based power and temperature GUI
■ Control registers for clocks
■ Control registers for remote system update
■ Control registers for SDI, SRAM, and fan speed.
■ Register with CPLD design revision and board information (read-only)
Clocks or Oscillators 2.5-V CMOS + LVDS 11 4 REFCLK
Power or Temperature Sense 2.5-V CMOS10 10 1 tempdiode_p, 1 tempdiode_n
Device I/O Total: 768
Table 2–4. Stratix IV GX Device Pin Count and Usage (Part 2 of 2)
Function I/O Standard I/O Count Special Pins
Table 2–5. Stratix IV GX Device EP4SGX530KF40 Features
ALMs
Equivalent
LEs
M9K
RAM
Blocks
M144K
Blocks MLAB
Blocks
Total
RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs
Transceivers
(8.5 Gbps,
3.2 Gbps)
Package
Type
212,480 531,200 1,280 64 10,624 27,376 1024 8 24, 12
1517-pin
Fineline BGA