Altera Arria V GT FPGA Development Board - Manual (Page 77)

Chapter 2: Board Components 2–67
Memory
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
Flash
The development board supports a 1 Gb CFI-compatible synchronous flash device for
non-volatile storage of FPGA configuration data, board information, test application
data, and user code space. This device is part of the shared FM bus that connects to
the flash memory and MAX II CPLD EPM2210 System Controller.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps. The write performance is 270 µs for a single word while
the erase time is 800 ms for a 128 K main block.
Table 2–35 lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Arria V GT FPGA in terms of I/O setting and
direction.
Table 2–35. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference (U4)
Schematic
Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description
F6 FLASH_ADVN AK30 1.8-V Address valid
B4 FLASH_CEN AU30 1.8-V Chip enable
E6 FLASH_CLK AL31 1.8-V Clock
F8 FLASH_OEN AN30 1.8-V Output enable
F7 FLASH_RDYBSYN AK32 1.8-V Ready
D4 FLASH_RESETN AL34 1.8-V Reset
G8 FLASH_WEN AN32 1.8-V Write enable
C6 FLASH_WPN — 1.8-V Write protect
A1 FM_A1 AT30 1.8-V Address bus
B1 FM_A2 AL30 1.8-V Address bus
C1 FM_A3 AP32 1.8-V Address bus
D1 FM_A4 AM34 1.8-V Address bus
D2 FM_A5 AJ33 1.8-V Address bus
A2 FM_A6 AK33 1.8-V Address bus
C2 FM_A7 AW33 1.8-V Address bus
A3 FM_A8 AH30 1.8-V Address bus
B3 FM_A9 AR30 1.8-V Address bus
C3 FM_A10 AP33 1.8-V Address bus
D3 FM_A11 AM31 1.8-V Address bus
C4 FM_A12 AP31 1.8-V Address bus
A5 FM_A13 AR31 1.8-V Address bus
B5 FM_A14 AT31 1.8-V Address bus
C5 FM_A15 AE29 1.8-V Address bus
D7 FM_A16 AG30 1.8-V Address bus
D8 FM_A17 AV31 1.8-V Address bus
A7 FM_A18 AW30 1.8-V Address bus
B7 FM_A19 AW31 1.8-V Address bus
C7 FM_A20 AV30 1.8-V Address bus