Altera Arria V GT FPGA Development Board - Manual (Page 50)

2–40 Chapter 2: Board Components
Components and Interfaces
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
42 HSMA_D1 AH16 2.5-V CMOS Dedicated CMOS I/O bit 1
43 HSMA_D2 AV13 2.5-V CMOS Dedicated CMOS I/O bit 2
44 HSMA_D3 AW13 2.5-V CMOS Dedicated CMOS I/O bit 3
47 HSMA_TX_D_P0 AV6 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4
48 HSMA_RX_D_P0 AW12 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5
49 HSMA_TX_D_N0 AV7 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6
50 HSMA_RX_D_N0 AV12 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7
53 HSMA_TX_D_P1 AU6 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8
54 HSMA_RX_D_P1 AR18 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9
55 HSMA_TX_D_N1 AT6 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10
56 HSMA_RX_D_N1 AP18 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11
59 HSMA_TX_D_P2 AU9 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12
60 HSMA_RX_D_P2 AU8 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13
61 HSMA_TX_D_N2 AT9 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14
62 HSMA_RX_D_N2 AU7 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15
65 HSMA_TX_D_P3 AV10 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16
66 HSMA_RX_D_P3 AW8 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17
67 HSMA_TX_D_N3 AU10 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18
68 HSMA_RX_D_N3 AW7 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19
71 HSMA_TX_D_P4 AU12 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20
72 HSMA_RX_D_P4 AW9 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21
73 HSMA_TX_D_N4 AT12 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22
74 HSMA_RX_D_N4 AV9 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23
77 HSMA_TX_D_P5 AP9 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24
78 HSMA_RX_D_P5 AU11 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25
79 HSMA_TX_D_N5 AN9 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26
80 HSMA_RX_D_N5 AT11 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27
83 HSMA_TX_D_P6 AP12 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28
84 HSMA_RX_D_P6 AR9 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29
85 HSMA_TX_D_N6 AN12 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30
86 HSMA_RX_D_N6 AT8 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31
89 HSMA_TX_D_P7 AM9 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32
90 HSMA_RX_D_P7 AW5 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33
91 HSMA_TX_D_N7 AL9 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34
92 HSMA_RX_D_N7 AW6 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35
95 HSMA_CLK_OUT_P1 AU13 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36
96 HSMA_CLK_IN_P1 AW4 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37
97 HSMA_CLK_OUT_N1 AT13 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38
Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board
Reference (J1)
Schematic Signal Name
Arria V GT
FPGA
Pin Number
I/O Standard Description