Altera Arria V GT FPGA Development Board - Manual (Page 30)

2–20 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
Setup Elements
The development board includes several different kinds of setup elements. This
section describes the following setup elements:
■ Board settings DIP switch
■ JTAG chain header switch
■ PCI Express control DIP switch
■ CPU reset push button
■ MAX II reset push button
■ Configuration push button
■ Image select push button
f For more information about the default settings of the DIP switches, refer to the
Arria V GT FPGA Development Kit User Guide .
Board Settings DIP Switch
The board settings DIP switch (SW5) controls various features specific to the board
and the MAX
II CPLD EPM2210 System Controller logic design. Table 2–8 lists the
switch controls and descriptions.
JTAG Settings DIP Switch
The JTAG settings DIP switch (SW6) either remove or include devices in the active
JTAG chain. However, the Arria V GT FPGAs and MAX
II CPLD EPM2210 System
Controller are always in the JTAG chain. Table 2–9 lists the switch controls and its
descriptions.
Table 2–8. Board Settings DIP Switch Controls
Switch
Schematic
Signal Name
Description
1 CLK_SEL
ON : 100 MHz clock select
OFF : SMA input clock select
2 CLK_ENABLE
ON : Enable on-board oscillators
OFF : Disable on-board oscillators
3 FACTORY_USER1
ON : Load the factory design from flash for Arria V FPGA 1 at power up
OFF : Load the user design from flash at power up
4 FACTORY_USER2 Unused
Table 2–9. JTAG Chain Header Switch Controls (Part 1 of 2)
Switch Schematic Signal Name Description
1 HSMA_JTAG_EN
ON : Bypass HSMA
OFF : HSMA in-chain
2 HSMB_JTAG_EN
ON : Bypass HSMB
OFF : HSMB in-chain